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M9OMS VLDO V1.1 vs V2 — Low-Dropout (LDO) Regulator Bench Comparison

A like-for-like bench comparison of the M9OMS VLDO V1.1 and V2 boards at the 12 V output setting. Both datasets are KC7XE bench measurements; this page uses only the input-voltage points common to both runs, with no interpolation or extrapolation, so each comparison is direct.

V2 is work in progress. The figures below are DC measurements on single samples of each board, taken at the board terminals. The dynamic measurements (transient response, loop characterisation, PSRR) listed under Validation Status are not addressed here.


Scope and method

Lower values indicate tighter regulation.


Results

ΔVOUT (mV) at each common input voltage, 12 V setting:

Vin (V) V1.1, 100 mA→1 A V2, 100 mA→1 A V1.1, 100 mA→2 A V2, 100 mA→2 A
8.0 collapse † 20 collapse † 50
9.0 300 20 1040 50
10.0 160 20 330 40
11.0 150 20 280 40
11.9 140 20 280 40
12.0 120 20 290 40
12.1 70 20 200 40
13.0 30 20 80 30
14.0 30 20 80 20
15.0 30 20 70 20
16.0 10 20 70 20

† At 8 V the V1.1 output does not hold under load (approximately 1.1 V at both 1 A and 2 A); V2 maintains regulation at approximately 8.0 V.

Two points on reading the table:


ΔVOUT vs input voltage

Load-induced output drop versus input voltage for V1.1 and V2 at 1 A and 2 A, 12 V setting

Load-induced ΔVOUT, 12 V setting. The shaded band marks V2's conservative dropout estimate (Vin ≤ 12.1 V at 1 A, ≤ 12.2 V at 2 A); the V1.1 dropout boundary has not been characterised. V1.1 markers above the scale are off-chart; "collapse" indicates loss of regulation at that load.

V2 maintains a near-constant ΔVOUT across the rated band — approximately 20 mV at 1 A and 40 mV at 2 A — down to the setpoint. V1.1 is comparable only above the setpoint and degrades as Vin falls, over the range a battery occupies as it discharges.


Mechanism: output voltage vs input voltage

Output voltage versus input voltage for V1.1 and V2 at 1 A and 2 A, 12 V setting

Output voltage versus input voltage, 12 V setting. V2 tracks the no-headroom line down to 8 V under load; V1.1 departs below ~9 V and is out of regulation at 8 V.

The ΔVOUT figures arise from two differences, both visible in the output-versus-input curves.

Dropout-region behaviour. Below the 12 V setpoint a linear regulator can only pass Vin less its own dropout. V2’s lower dropout allows it to deliver close to the full input voltage at 1–2 A down to 8 V. V1.1 requires more headroom: under load its output departs from the input at around 11–12 V and is out of regulation by 8 V. For a 3S LiPo under transmit load, this determines how far down the discharge curve the supply remains usable.

Pass-device conduction at higher current. At 2 A the V2 pass device drops less and is driven harder, so its 2 A ΔVOUT (~40 mV) remains close to its 1 A ΔVOUT (~20 mV). V1.1’s 2 A ΔVOUT is 2–3× its 1 A figure in regulation and increases further in the dropout region as gate drive becomes insufficient — the same mechanism behind the loss of regulation at 8 V.

Regulation knee (11–14 V)

Zoomed output-versus-input view from 11 to 14 V showing each board's 100 mA, 1 A and 2 A traces through the regulation knee

Regulation knee, 11–14 V. Each board's 100 mA, 1 A and 2 A traces are shown; ΔVOUT is the vertical separation between a board's light-load trace and its loaded traces, which is independent of each board's trim.

Plotting all three load traces shows the behaviour in detail. V2’s 100 mA, 1 A and 2 A traces remain within approximately 40 mV of one another up to and through the knee, reaching the plateau by ~12.1 V. V1.1’s traces separate below ~12 V — at 12.0 V the 2 A output has fallen approximately 290 mV below the 100 mA trace — and the board does not fully settle until ~13 V. A 12 V output taken from a nominal 12 V battery operates within this window.


Summary

For the full V2 dataset (all three output settings, thermal, drift) see Bench Measurements; for the design rationale and the V1.1 → V2 change list see the project README.


Comparison data: Stan Dye, KC7XE. V1.1 and V2 measured by the same method, at the board terminals, single sample of each board. Plots generated from the tabulated data above.